FPGA Implementation of Network-on-Chip Router Architecture for Multicore-SoC Communication Paradigm

In the deep submicron era, the downscaling of silicon technology and the possibility of building multiprocessor System-on-Chip (MPSoCs) makes intrachip communication, a key challenge in the gigascale chip designing process. Performance and power of gigascale System-on-Chip(SoC) is mainly communication dominated. SoC communication architectures start facing scalability as well as modularity limitations and more advanced bus specifications are emerging to deal with these issues at the expense of silicon area and complexity. To overcome the scalability limitations, Network-on-Chip paradigm is currently viewed as a innovative approach to provide a high performance, scalable and robust infrastructure for on-chip communication. This paper presents a Networkon-Chip router architecture for intrachip communication of SoC architectures. The router is designed using VHDL language and implemented on Virtex6 FPGA with the help of Integrated Software Environment ISE 14.5. The simulation and synthesis results are also presented. KeywordsNoC, SoC , VHDL, Router, FPGA